WT6014
Digital Monitor Controller
Ver. 1.21 Jul-31-1998
Pull low SCL
SCL
SDA
In
1 01 0 00 0 0
SDA
Out
A
Write REG#19H to release SCL
Shift register to data buffer
INT0
Data Byte
Pull low SCL
Pull low SCL
Data Byte
A
A
DDC2B=1
ADDR=0
R/W=0
START=1
STOP=0
DDC2B=1
ADDR=0
R/W=0
START=0
STOP=0
DDC2B state write timing
DDC2B=1
ADDR=0
R/W=0
START=0
STOP=0
DDC2B=1
ADDR=0
R/W=0
START=0
STOP=1
Pull low SCL
SCL
SDA
In
1 01 0 00 0 1
SDA
Out
A
Write REG#19H to release SCL
Data buffer to shift reg
INT0
Data Byte
Pull low SCL
A
Data Byte
DDC2B=1
ADDR=0
R/W=1
START=1
STOP=0
DDC2B=1
ADDR=0
R/W=1
START=0
STOP=0
DDC2B state read timing
N
DDC2B=1
ADDR=0
R/W=1
START=0
STOP=1
Weltrend Semiconductor, Inc.
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