ADSP-21367 View Datasheet(PDF) - Analog Devices
Part Name
Description
View to exact match
ADSP-21367 Datasheet PDF : 56 Pages
| |||
ADSP-21367/ADSP-21368/ADSP-21369
S/PDIF Transmitter Input Data Timing
The timing requirements for the input port are given in
Table 38. Input signals (SCLK, FS, SDATA) are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Table 38. S/PDIF Transmitter Input Data Timing
Parameter
Min
Max
Unit
Timing Requirements
t1
SISFS
FS Setup Before SCLK Rising Edge
3
ns
t1
SIHFS
FS Hold After SCLK Rising Edge
3
ns
t1
SISD
SData Setup Before SCLK Rising Edge
3
ns
t1
SIHD
SData Hold After SCLK Rising Edge
3
ns
tSISCLKW
Clock Width
36
ns
tSISCLK
Clock Period
80
ns
tSITXCLKW
Transmit Clock Width
9
ns
tSITXCLK
Transmit Clock Period
20
ns
1 DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
DAI_P20-1
(TXCLK)
tSITXCLKW
tSITXCLK
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(SDATA)
tSISCLKW
tSISFS
tSISD
Figure 32. S/PDIF Transmitter Input Timing
Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This TxCLK
input is divided down to generate the biphase clock.
Table 39. Oversampling Clock (TxCLK) Switching Characteristics
Parameter
Min
TxCLK Frequency for TxCLK = 384 × FS
TxCLK Frequency for TxCLK = 256 × FS
Frame Rate
tSIHFS
tSIHD
Max
73.8
49.2
192.0
Unit
MHz
MHz
kHz
Rev. C | Page 40 of 56 | January 2008
|
|
Share Link: 