ADSP-21367/ADSP-21368/ADSP-21369
Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and it
should meet setup and hold times with regard to SCLK on the
output port. The serial data output, SDATA, has a hold time
and delay specification with regard to SCLK. Note that SCLK
rising edge is the sampling edge and the falling edge is the
drive edge.
Table 37. SRC, Serial Output Port
Parameter
Min
Max
Unit
Timing Requirements
t1
SRCSFS
t1
SRCHFS
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
tSRCCLKW
Clock Width
tSRCCLK
Clock Period
Switching Characteristics
t1
SRCTDD
t1
SRCTDH
Transmit Data Delay After SCLK Falling Edge
Transmit Data Hold After SCLK Falling Edge
4
ns
5.5
ns
9
ns
20
ns
9.9
ns
1
ns
1 DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(SDATA)
SAMPLE EDGE
tSRCCLK
tSRCCLKW
tSRCSFS
tSRCHFS
tSRCTDD
tSRCTDH
Figure 28. SRC Serial Output Port Timing
Rev. C | Page 38 of 56 | January 2008