ADSP-21367/ADSP-21368/ADSP-21369
SDRAM Interface Timing (166 MHz SDCLK)
The 166 MHz access speed is for a single processor. When mul-
tiple ADSP-21368 processors are connected in a shared memory
system, the access speed is 100 MHz.
Table 23. SDRAM Interface Timing1
Parameter
Timing Requirements
tSSDAT
DATA Setup Before SDCLK
tHSDAT
DATA Hold After SDCLK
Switching Characteristics
tSDCLK
tSDCLKH
tSDCLKL
tDCAD
tHCAD
tDSDAT
tENSDAT
SDCLK Period
SDCLK Width High
SDCLK Width Low
Command, ADDR, Data Delay After SDCLK2
Command, ADDR, Data Hold After SDCLK2
Data Disable After SDCLK
Data Enable After SDCLK
1 For fCCLK = 400 MHz (SDCLK ratio = 1:2.5).
2 Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.
Min
Max
500
1.23
6.0
2.6
2.6
4.8
1.2
5.3
1.3
SDCLK
DATA (IN)
DATA(OUT)
CMND ADDR
(OUT)
tSSDAT
tSDCLK
tSDCLKH
tH SDAT
tSDCLKL
tENSDAT
tDC AD
tDSDAT
tHCAD
tDCAD
tHCAD
Figure 16. SDRAM Interface Timing
Unit
ps
ns
ns
ns
ns
ns
ns
ns
ns
Rev. C | Page 26 of 56 | January 2008