ADSP-21367 View Datasheet(PDF) - Analog Devices
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ADSP-21367 Datasheet PDF : 56 Pages
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ADSP-21367/ADSP-21368/ADSP-21369
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing param-
eters and switching characteristics apply to external DAI pins
(DAI_P01–20).
Table 21. Precision Clock Generator (Direct Pin Routing)
Parameter
Min
Max
Unit
Timing Requirements
tPCGIP
Input Clock Period
20
ns
tSTRIG
PCG Trigger Setup Before Falling
4.5
ns
Edge of PCG Input Clock
tHTRIG
PCG Trigger Hold After Falling
3
ns
Edge of PCG Input Clock
Switching Characteristics
tDPCGIO
PCG Output Clock and Frame Sync Active Edge 2.5
10
ns
Delay After PCG Input Clock
tDTRIGCLK
PCG Output Clock Delay After PCG Trigger
2.5 + (2.5 × tPCGIP)
10 + (2.5 × tPCGIP)
ns
tDTRIGFS
PCG Frame Sync Delay After PCG Trigger
2.5 + ((2.5 – PH) × tPCGIP)
10 + ((2.5 – PH) × tPCGIP)
ns
t1
PCGOW
Output Clock Period
2 × tPCGIP – 1
ns
PH = FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21368 Processor, “Precision Clock
Generators” chapter.
1 In normal mode.
tSTRIG
DAI_Pn
DPI_Pn
PCG_TRIGx_I
DAI_Pm
DPI_Pm
PCG_EXTx_I
(CLKIN)
DAI_Py
DPI_Py
PCG_CLKx_O
tHTRIG
tDPCGIO
tDTRIGCLK
tPCGIP
tDPCGIO
DAI_Pz
DPI_Pz
PCG_FSx_O
tDTRIGFS
Figure 14. Precision Clock Generator (Direct Pin Routing)
tPCGOW
Rev. C | Page 24 of 56 | January 2008
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