ADSP-21367 View Datasheet(PDF) - Analog Devices

Part Name

Description

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ADSP-21367

SHARC Processors

Analog Devices 

PACKAGE INFORMATION

The information presented in Figure 3 provides details about

the package branding for the ADSP-21367/ADSP-21368/

ADSP-21369 processors. For a complete listing of product avail-

ability, see Ordering Guide on Page 55.

a

ADSP-2136x

tppZ-cc

vvvvvv.x n.n

yyww country_of_origin

S

Figure 3. Typical Package Brand

Table 9. Package Brand Information

Brand Key

t

pp

Z

cc

vvvvvv.x

n.n

yyww

Field Description

Temperature Range

Package Type

RoHS Compliant Option (optional)

See Ordering Guide

Assembly Lot Code

Silicon Revision

Date Code

ESD CAUTION

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

MAXIMUM POWER DISSIPATION

See Engineer-to-Engineer Note (EE-299) for detailed thermal

and power information regarding maximum power dissipation.

For information on package thermal specifications, see Thermal

Characteristics on Page 48.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 10 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

ADSP-21367/ADSP-21368/ADSP-21369

Table 10. Absolute Maximum Ratings

Parameter

Internal (Core) Supply Voltage (VDDINT)

Analog (PLL) Supply Voltage (AVDD)

External (I/O) Supply Voltage (VDDEXT)

Input Voltage

Output Voltage Swing

Load Capacitance

Storage Temperature Range

Junction Temperature Under Bias

Rating

–0.3 V to +1.5 V

–0.3 V to +1.5 V

–0.3 V to +4.6 V

–0.5 V to +3.8 V

–0.5 V to VDDEXT + 0.5 V

200 pF

–65°C to +150°C

125°C

TIMING SPECIFICATIONS

The processor’s internal clock (a multiple of CLKIN) provides

the clock signal for timing internal memory, processor core, and

serial ports. During reset, program the ratio between the proces-

sor’s internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG1–0 pins (see Table 8 on Page 15).

To determine switching frequencies for the serial ports, divide

down the internal clock, using the programmable divider con-

trol of each port (DIVx for the serial ports).

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL).

This PLL-based clocking minimizes the skew between the sys-

tem clock (CLKIN) signal and the processor’s internal clock.

Note the definitions of various clock periods that are a function

of CLKIN and the appropriate ratio control shown in Table 11

and Table 12.

In Table 11, CCLK is defined as:

fCCLK = (2 × PLLM × fINPUT) ÷ (2 × PLLN)

where:

fCCLK = CCLK frequency

PLLM = Multiplier value programmed

PLLN = Divider value programmed

Table 11. ADSP-21368 Clock Generation Operation

Timing

Requirements

CLKIN

CCLK

Description

Input Clock

Core Clock

Calculation

1/tCK

1/tCCLK

Note the definitions of various clock periods shown in Table 12

which are a function of CLKIN and the appropriate ratio con-

trol shown in Table 11.

Rev. C | Page 17 of 56 | January 2008

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