DS2761 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

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DS2761

High-Precision Li+ Battery Monitor

Maxim Integrated 

DS2761

a command sequence from proceeding as a result of a CRC mismatch. Proper use of the CRC can result

in a communication channel with a very high level of integrity.

The CRC can be generated by the host using a circuit consisting of a shift register and XOR gates as

shown in Figure 10, or it can be generated in software. Additional information about the Dallas 1-Wire

CRC is available in Application Note 27, Understanding and Using Cyclic Redundancy Checks with

Dallas Semiconductor Touch Memory Products. (This application not can be found on the Maxim/Dallas

Semiconductor website at www.maxim-ic.com).

In the circuit in Figure 14, the shift register bits are initialized to 0. Then, starting with the least

significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has

been entered, then the serial number is entered. After the 48th bit of the serial number has been entered,

the shift register contains the CRC value.

Figure 14. 1-WIRE CRC GENERATION BLOCK DIAGRAM

MSb

XOR

XOR

INPUT

LSb

XOR

HARDWARE CONFIGURATION

Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive

it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the

bus with open-drain or tri-state output drivers. The DS2761 used an open-drain output driver as part of

the bidirectional interface circuitry shown in Figure 15. If a bidirectional pin is not available on the bus

master, separate output and input pins can be connected together.

The 1-Wire bus must have a pullup resistor at the bus-master end of the bus. For short line lengths, the

value of this resistor should be approximately 5kW. The idle state for the 1-Wire bus is high. If, for any

reason, a bus transaction must be suspended, the bus must be left in the idle state in order to properly

resume the transaction later. If the bus is left low for more than 120ms, slave devices on the bus begin to

interpret the low period as a reset pulse, effectively terminating the transaction.

Figure 15. 1-WIRE BUS INTERFACE CIRCUITRY

BUS MASTER

Vpullup

(2.0V to 5.5V)

DS2761 1-WIRE PORT

4.7kW

Rx

Rx

1mA

Tx

(typ)

Tx

Rx = RECEIVE

Tx = TRANSMIT

100W

MOSFET

15 of 24

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