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J112 View Datasheet(PDF) - InterFET

Part Name
Description
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J112 Datasheet PDF : 1 Pages
1
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B-51
J111, J112, J113
N-Channel Silicon Junction Field-Effect Transistor
Absolute maximum ratings at TA = 25¡C
Reverse Gate Source & Reverse Gate Drain Voltage
Continuous Forward Gate Current
Continuous Device Power Dissipation
Power Derating
– 35 V
50 mA
360 mW
3.27 mW/°C
At 25°C free air temperature
Static Electrical Characteristics
Gate Source Breakdown Voltage
Gate Reverse Current
Gate Source Cutoff Voltage
Drain Saturation Current (Pulsed)
Drain Cutoff Current
Dynamic Electrical Characteristics
Drain Source ON Resistance
Drain Gate Capacitance
Source Gate Capacitance
Drain Gate + Source Gate Capacitance
Switching Characteristics
Turn ON Delay Time
Rise Time
Turn OFF Delay Time
Fall Time
V(BR)GSS
IGSS
VGS(OFF)
IDSS
ID(OFF)
rds(on)
Cdg
Cgs
Cgd + Cgs
td(on)
tr
td(off)
tf
J111
J112
J113
Min Max Min Max Min Max Unit
– 35
– 35
– 35
V
–1
–1
– 1 nA
– 3 – 10 – 1 – 5
–3 V
20
5
2
mA
–1
–1
– 1 nA
30
5
5
28
Typ
7
6
20
15
50
5
5
28
Typ
7
6
20
15
100
5 pF
5 pF
28 pF
Typ
7
ns
2
ns
20
ns
15
ns
Process NJ132
Test Conditions
IG = – 1µA, VDS = ØV
VGS = – 15V, VDS = ØV
VDS = 5V, ID = 1 µA
VDS = 15V, VGS = ØV
VDS = 15V, VGS = – 10V
VGS = ØV, VDS = 0.1V
VDS = ØV, VGS = – 10V
VDS = ØV, VGS = – 10V
VDS = VGS = ØV
f = 1 kHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
J111 J112 J113
VDD
10
10
10 V
VGS(OFF) – 12
–7
–5 V
RL
800 1600 3200
TOÐ226AA Package
Dimensions in Inches (mm)
Pin Configuration
1 Drain, 2 Source, 3 Gate
www.interfet.com
Surface Mount
SMPJ111, SMPJ112, SMPJ113
1000 N. Shiloh Road, Garland, TX 75042
(972) 487-1287 FAX (972) 276-3375
 

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