|DRV2605L-Q1||Automotive Haptic Driver for LRA and ERM with Effect Library and Smart-Loop Architecture|
|DRV2605L-Q1 Datasheet PDF : 67 Pages |
SLOS874A – OCTOBER 2015 – REVISED OCTOBER 2015
7.6.21 Control1 (Address: 0x1B)
Figure 49. Control1 Register
Table 24. Control1 Register Field Descriptions
This bit applies higher loop gain during overdrive to enhance actuator transient response.
This bit applies a 0.9-V common mode voltage to the IN/TRIG pin when an AC-
coupling capacitor is used. This bit is only useful for analog input mode. This bit
should not be asserted for PWM mode or external trigger mode.
0: Common-mode drive disabled for DC-coupling or digital inputs modes
1: Common-mode drive enabled for AC coupling
LRA Mode: Sets initial guess for LRA drive-time in LRA mode. Drive time is
automatically adjusted for optimum drive in real time; however, this register
should be optimized for the approximate LRA frequency. If the bit is set too low,
it can affect the actuator startup time. If it is set too high, it can cause instability.
Optimum drive time (ms) ≈ 0.5 × LRA Period
Drive time (ms) = DRIVE_TIME[4:0] × 0.1 ms + 0.5 ms
ERM Mode: Sets the sample rate for the back-EMF detection. Lower drive times
cause higher peak-to-average ratios in the output signal, requiring more supply
headroom. Higher drive times cause the feedback to react at a slower rate.
Drive Time (ms) = DRIVE_TIME[4:0] × 0.2 ms + 1 ms
Copyright © 2015, Texas Instruments Incorporated
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