ISD4002_07 View Datasheet(PDF) - Winbond
Part Name
Description
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ISD4002_07 Datasheet PDF : 38 Pages
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ISD4002 SERIES
PIN NAME
XCLK
SCLK
PIN NO.
SOIC /
PDIP
TSOP
26
6
28
8
FUNCTION
External Clock Input: The ISD4002 series is configured at
the factory with an internal sampling clock frequency
centered to ±1 percent of specification. The frequency is
then maintained to a variation of ±2.25 percent over the
entire commercial temperature and operating voltage
ranges. The internal clock has a –6/+4 percent tolerance
over the industrial temperature and voltage ranges. A
regulated power supply is recommended for industrial
temperature range parts. If greater precision is required,
the device can be clocked through the XCLK pin as follows:
Part Number
Sample Rate
Required Clock
ISD4002-120
8.0 kHz
1024 kHz
ISD4002-150
6.4 kHz
819.2 kHz
ISD4002-180
5.3 kHz
682.7 kHz
ISD4002-240
4.0 kHz
512 kHz
These recommended clock rates should not be varied
because the anti-aliasing and smoothing filters are fixed.
Otherwise, aliasing problems can occur if the sample rate
differs from the one recommended. The duty cycle on the
input clock is not critical, as the clock is immediately
divided by two. If the XCLK is not used, this input must
be connected to ground.
Serial Clock: This is the input clock to the ISD4002 device.
It is generated by the master device (typically
microcontoller) and is used to synchronize the data transfer
in and out of the device through the MOSI and MISO lines,
respectively. Data is latched into the ISD4002 on the rising
edge of SCLK and shifted out of the device on the falling
edge of SCLK.
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