256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Recommended DC Operation Ranges
Table 23: IDD Operating Conditions and Maximum Limits
+0°C ≤ TC ≤ +95°C; VDD = MAX unless otherwise noted
Description
Conditions
Symbol
-33
Standby current tCK = Idle
ISB1 (VDD) X32
59
All banks idle, no inputs toggling
ISB1 (VDD) X16
55
ISB1 (VEXT)
12
Active standby
tCK = MIN, CS# = 1
ISB2 (VDD) X32
280
current
No commands, half address/data toggle ISB2 (VDD) X16
255
up to once every 4 clock cycles
ISB2 (VEXT)
12
Incremental
BL = 2, tCK = MIN, tRC = MIN,
IDD1 (VDD) X32
287
current
1 bank active, half address data toggles IDD1 (VDD) X16
263
once per tRC, read followed by write
IDD1 (VEXT)
16
sequence
Incremental
BL = 4, tCK = MIN, tRC = MIN,
IDD2 (VDD) X32
341
current
1 bank active, half address/data toggle IDD2 (VDD) X16
285
once per tRC, read followed by write
IDD2 (VEXT)
20
sequence
Burst refresh
tCK = MIN, tRC = MIN
IREF1 (VDD) X32
460
current
Cyclic bank refresh, data inputs are
IREF1 (VDD) X16
451
switching
IREF1 (VEXT)
79
Distributed
tCK = MIN, tRC = MIN
IREF2 (VDD) X32
282
refresh current Single bank refresh, half address/data IREF2 (VDD) X16
265
toggle
IREF2 (VEXT)
20
Operating supply BL = 2, tCK = MIN, 8 bank cyclic access, IDD2W(VDD) X32
807
current example half of address bits change every 4 clock IDD2W (VDD) X16 713
cycles, continuous data
IDD2W(VEXT)
46
Operating supply BL = 4, tCK = MIN, 8 bank cyclic access, IDD4W (VDD) X32 723
current example half of address bits change every 2
clocks, continuous data
IDD4W (VDD) X16
549
IDD4W (VEXT)
46
Max
-4
59
55
12
271
244
12
266
243
16
326
273
20
431
419
68
268
254
20
706
616
40
634
476
40
-5
Units
59
mA
55
12
228
mA
205
12
240
mA
221
16
300
mA
250
20
357
mA
347
57
249
mA
231
20
598
mA
519
34
521
mA
392
34
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
37
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©2001 Micron Technology, Inc. All rights reserved.