MT49H16M16 View Datasheet(PDF) - Micron Technology

Part Name

Description

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MT49H16M16

REDUCED LATENCY DRAM (RLDRAM®)

Micron Technology 

256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM

Tap Instruction Set

Tap Instruction Set

Overview

Eight different instructions are possible with the three-bit instruction register. All com-

binations are listed in the Instruction Codes table (see page 33). Three of these instruc-

tions are listed as RESERVED and should not be used. The other five instructions are

described in detail below.

The TAP controller used in this RLDRAM is not fully compliant to the 1149.1 convention

because some of the mandatory 1149.1 instructions are not fully implemented. The TAP

controller cannot be used to load address, data or control signals into the RLDRAM and

cannot preload the I/O buffers. The RLDRAM does not implement the 1149.1 com-

mands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it per-

forms a capture of the I/O ring when these instructions are executed.

Instructions are loaded into the TAP controller during the Shift-IR state when the

instruction register is placed between TDI and TDO. During this state, instructions are

shifted through the instruction register through the TDI and TDO balls. To execute the

instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR

state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruc-

tion register is loaded with all zeros. EXTEST is not implemented in the TAP controller,

hence this device is not IEEE 1149.1 compliant.

The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is

loaded into the instruction register, the RLDRAM responds as if a SAMPLE/PRELOAD

instruction has been loaded. EXTEST does not place the RLDRAM outputs in a High-Z

state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the

instruction register. It also places the instruction register between the TDI and TDO

balls and allows the IDCODE to be shifted out of the device when the TAP controller

enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register upon power-up or when-

ever the TAP controller is given a test logic reset state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this

instruction is not implemented, so the device TAP controller is not fully 1149.1-

compliant.

When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the

TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirec-

tional balls is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up

to 50 MHz, while the RLDRAM clock operates significantly faster. Because there is a large

difference in the clock frequencies, it is possible that during the Capture-DR state, an

input or output will undergo a transition. The TAP may then try to capture a signal while

in transition (metastable state). This will not harm the device, but there is no guarantee

as to the value that will be captured. Repeatable results may not be possible.

pdf: 09005aef81121545/source: 09005aef810c0ffc

256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN

30

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001 Micron Technology, Inc. All rights reserved.

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