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JS28F128P30BF65 View Datasheet(PDF) - Numonyx -> Micron

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JS28F128P30BF65 Datasheet PDF : 90 Pages
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P30-65nm SBC
1.0
1.1
1.2
Functional Description
Introduction
This document provides information about the Numonyx® AxcellTM P30-65nm Single Bit
per Cell (SBC) Flash memory and describes its features, operations, and specifications.
P30-65nm SBC device is offered in 64-Mbit and 128-Mbit. Benefits include high-speed
interface NOR device, and support for code and data storage. Features include high-
performance synchronous-burst read mode, a dramatical improvement in buffer
program time through larger buffer size, fast asynchronous access times, low power,
flexible security options, and three industry-standard package choices.
P30-65nm SBC device is manufactured using 65nm process technology.
Overview
P30-65nm SBC device provides high performance on a 16-bit data bus. Individually
erasable memory blocks are sized for optimum code and data storage. Upon initial
power-up or return from reset, the device defaults to asynchronous page-mode read.
Configuring the Read Configuration Register (RCR) enables synchronous burst-mode
reads. In synchronous burst mode, output data is synchronized with a user-supplied
clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the device incorporates
technology that enables fast buffer program and erase operations. The device features
a 256-word buffer to enable optimum programming performance, which can improve
system programming throughput time significantly to 1.8MByte/s.
Designed for low-voltage systems, the P30-65nm SBC device supports read operations
with VCC at 1.8V, and erase and program operations with VPP at 1.8V or 9.0V. Buffered
Enhanced Factory Programming provides the fastest flash array programming
performance with VPP at 9.0V, which increases factory throughput with 3.2Mbyte/s.
With VPP at 1.8V, VCC and VPP can be tied together for a simple, ultra low power
design. In addition to voltage flexibility, a dedicated VPP connection provides complete
data protection when VPP VPPLK.
The Command User Interface is the interface between the system processor and all
internal operations of the device. An internal Write State Machine automatically
executes the algorithms and timings necessary for block erase and program. A Status
Register indicates erase or program completion and any errors that may have occurred.
A device command sequence invokes program and erase automation. Each erase
operation erases one block. The Erase Suspend feature allows system software to
pause an erase cycle to read or program data in another block. Program Suspend
allows system software to pause programming to read other locations.
The OTP Register allows unique flash device identification that can be used to increase
system security. The individual Block Lock feature provides zero-latency block locking
and unlocking. The P30-65nm SBC device adds enhanced protection via Password
Access; this new feature allows write and/or read access protection of user-defined
blocks. In addition, the P30-65nm SBC device also has backward-compatible One-Time
Programmable (OTP) permanent block locking security feature.
Datasheet
5
Apr 2010
Order Number:208033-02
 

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