datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

T-8208-BAL-DT View Datasheet(PDF) - Agere -> LSI Corporation

Part Name
Description
View to exact match
T-8208-BAL-DT
Agere
Agere -> LSI Corporation Agere
T-8208-BAL-DT Datasheet PDF : 214 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Advance Data Sheet
September 2001
CelXpres T8208
ATM Interconnect
Table of Contents (continued)
Contents
Page
10.4 Cell Bus Arbitration ................................................................................................................................. 67
10.5 Cell Bus Monitoring................................................................................................................................. 68
10.6 GTL+ Logic ............................................................................................................................................. 68
10.7 Cell Bus Write and Read Clocks ............................................................................................................. 69
10.8 Modify Cell Bus Request Priority Based on RX PHY FIFO Threshold.................................................... 70
10.9 Digital Loopback Before Cell Bus ........................................................................................................... 70
11 SDRAM Interface.............................................................................................................................................. 71
11.1 Memory Configuration............................................................................................................................. 71
11.2 Powerup Sequence................................................................................................................................. 71
11.3 SDRAM Interface Timing ........................................................................................................................ 72
11.4 Queuing .................................................................................................................................................. 73
11.5 SDRAM Refresh ..................................................................................................................................... 80
11.6 SDRAM Throughput................................................................................................................................ 81
12 Traffic Management.......................................................................................................................................... 82
12.1 Cell Loss Priority (CLP)........................................................................................................................... 82
12.2 Forward Explicit Congestion Notification (FECN) ................................................................................... 82
12.3 Partial Packet Discard (PPD) .................................................................................................................. 83
13 JTAG Test Access Port .................................................................................................................................... 84
13.1 Instruction Register ................................................................................................................................. 84
13.2 Boundary-Scan Register ......................................................................................................................... 85
14 Registers........................................................................................................................................................... 88
14.1 Register Types........................................................................................................................................ 88
14.2 Direct Memory Access Registers ............................................................................................................ 92
14.2.1 Little-Endian Format (big_end = 0) for Extended Memory Access Registers 30h—37h............ 97
14.2.2 Big-Endian Format (big_end = 1) for Extended Memory Access Registers 30h—37h .............. 99
14.2.3 General-Purpose I/O Control Registers ................................................................................... 101
14.2.4 Control Cells ............................................................................................................................ 102
14.2.5 Multicast Memories .................................................................................................................. 103
14.3 Extended Memory Registers.................................................................................................................103
14.3.1 Main Registers ......................................................................................................................... 103
14.3.2 UTOPIA Registers ................................................................................................................... 125
14.3.2.1 TX UTOPIA Configuration ......................................................................................... 130
14.3.2.2 TX UTOPIA Monitoring .............................................................................................. 175
14.3.2.3 RX UTOPIA Count Monitoring ................................................................................... 176
14.3.2.4 RX UTOPIA Configuration Monitoring ....................................................................... 177
14.3.3 SDRAM Registers .................................................................................................................... 179
14.3.3.1 SDRAM Control Memory ........................................................................................... 187
14.3.4 Various Internal Memories ....................................................................................................... 190
14.3.4.1 Control Cell Memories ............................................................................................... 190
14.3.4.2 Multicast Number Memories ...................................................................................... 191
14.3.4.3 PPD State Memory ....................................................................................................193
14.3.5 Dropped Cell Count .................................................................................................................194
14.3.6 External Memories ................................................................................................................... 197
14.3.6.1 Look-Up Translation Memory .................................................................................... 197
14.3.6.2 SDRAM Buffer Memory .............................................................................................197
15 Absolute Maximum Ratings ............................................................................................................................ 198
16 Recommended Operating Conditions............................................................................................................. 198
17 Handling Precautions...................................................................................................................................... 198
18 Electrical Requirements and Characteristics .................................................................................................. 199
18.1 Crystal Information................................................................................................................................ 199
18.2 dc Electrical Characteristics .................................................................................................................. 200
Agere Systems Inc.
3
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]