KSZ8765CLXCC View Datasheet(PDF) - Micrel

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KSZ8765CLXCC

Integrated 5-Port 10/100 Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces

Micrel 

Micrel, Inc.

KSZ8765CLX

The RGMII interface operates at up to a 1Gbps speed rate. Additional transmit and receive signals control the different

directions of data transfer. This RGMII interface supports RGMII Rev. 2.0 with adjustable ingress clock and egress clock

delay by Register 86 (0x56).

For proper RGMII configuration with the connection partner, the Register 86 (0x56) bits [4:3] need to setup correctly. A

configuration table is shown below.

Table 10. Port 5 SW5-RGMII Clock Delay Configuration with Connection Partner

KSZ8765 Register 86

Bits [4:3]

Configuration

RGMII Clock Mode

(Receive and Transmit)

KSZ8765

Register 86 (0x56)

KSZ8765 RGMII Clock

Delay/Slew

Configuration

Bit [4:3] = 11 Mode

Ingress Clock Input

Egress Clock Output

Bit [4] = 1

Bit [3] = 1

Delay

Delay

Bit [4:3] = 10 Mode

Ingress Clock Input

Egress Clock Output

Bit [4] = 1

Bit [3] = 0

Delay

No Delay

Bit [4:3] = 01 Mode

Ingress Clock Input

Egress Clock Output

Bit [4] = 0 (default)

Bit [3] = 1 (default)

No Delay

Delay

Bit [4:3] = 00 Mode

Ingress Clock Input

Egress Clock Output

Bit [4] = 0

Bit [3] = 0

No Delay

No Delay

Note:

5. A processor with RGMII, an external GPHY, or KSZ8765 back-to-back connection.

Connection Partner

RGMII Clock

Configuration(5)

No Delay

No Delay

No Delay

Delay

Delay

No Delay

Delay

Delay

For example, two KSZ8765 devices are the back-to-back connection. If one device set bit [4:3] = ’11’, another one should

set bit [4:3] = ‘00’. If one device set bit [4:3] =’01’, another one should set bit [4:3] = ‘01’ too.

The RGMII mode is configured by the strap-in Pin LED3 [1:0] = ’11’ (default) or Register 86 (0x56) bits [1:0] = ‘11’

(default). The speed choice is set by the strap-in pin LED1_0 or Register 86 (0x56) bit [6], the default speed is 1Gbps with

bit [6] = ‘1’, set bit [6] = ‘0’ is for 10/100Mbps speed in RGMII mode. KSZ8765CLX provides Register 86 bits [4:3] with the

adjustable clock delay and Register 164 bits [6:4] with the adjustable drive strength for best RGMII timing on board level in

1Gbps mode.

Port 5 GMAC5 SW5-RMII Interface

The reduced media independent interface (RMII) specifies a low pin count media independent interface (MII). The

KSZ8765CLX supports RMII interface on Port 5 and provides the following key characteristics:

 Supports 10Mbps and 100Mbps data rates.

 Uses a single 50MHz clock reference (provided internally or externally): In internal mode, the chip provides a

reference clock from the RXC5 pin to the opposite clock input pin for RMII interface when Port 5 RMII is set to clock

mode.

 In external mode, the chip receives 50MHz reference clock on the TXC5/REFCLKI5 pin from an external oscillator or

opposite RMII interface when the device is set to normal mode.

 Provides independent 2-bit wide (bi-bit) transmit and receive data paths.

For the details of SW5-RMII (Port 5 GMAC5 RMII) signal connection, see the table below:

When the device is strapped to normal mode, the reference clock comes from the TXC5/REFCLKI5 pin and will be used

as the device’s clock source. The strap pin LED1_1 can select the device’s clock source either from the TXC5/REFCLKI5

pin or from an external 25MHz crystal/oscillator clock on the XI/XO pin.

In internal mode, when using an internal 50MHz clock as SW5-RMII reference clock, the KSZ8765CLX Port 5 should be

set to clock mode by the strap pin LED2_1 or the port Register 86 bit 7. The clock mode of the KSZ8765CLX device will

provide the 50MHz reference clock to the Port 5 RMII interface.

July 23, 2014

42

Revision 1.0

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