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KSZ8765CLXCC View Datasheet(PDF) - Micrel

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KSZ8765CLXCC Datasheet PDF : 153 Pages
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Micrel, Inc.
KSZ8765CLX
Features
Management Capabilities
The KSZ8765CLX includes all the functions of a
10/100Base-T/TX and 100Base-FX switch system,
which combines a switch engine, frame buffer
management, address look-up table, queue
management, MIB counters, media access controllers
(MAC), and PHY transceivers
Non-blocking store-and-forward switch fabric assures
fast packet delivery by utilizing 1024-entry forwarding
table
Port mirroring/monitoring/sniffing: ingress and/or egress
traffic to any port
MIB counters for fully compliant statistics gathering - 36
counters per port
Hardware support for port-based flush and freeze
command in MIB counter.
Multiple loopback of remote, PHY, and MAC modes
support for the diagnostics
Rapid spanning tree support (RSTP) for topology
management and ring/linear recovery
Robust PHY Ports
Four integrated IEEE 802.3/802.3u-compliant Ethernet
transceivers supporting 10Base-T and 100Base-TX
802.1az EEE supported
On-chip termination resistors and internal biasing for
differential pairs to reduce power
HP Auto MDI/MDI-X™ crossover support eliminates the
need to differentiate between straight or crossover
cables in applications
MAC and GMAC Ports
Four internal media access control (MAC1 to MAC4)
units and one internal Gigabit media access control
(GMAC5) unit
GMII, RGMII, MII, or RMII interfaces support for the Port
5 GMAC5 with uplink
2kb jumbo packet support
Tail tagging mode (one byte added before FCS) support
on Port 5 to inform the processor which ingress port
receives the packet and its priority
Supports reduced media independent interface (RMII)
with 50MHz reference clock output
Supports media independent interface (MII) in either
PHY mode or MAC mode on Port 5
Micrel LinkMD® cable diagnostic capabilities for
determining cable opens, shorts, and length
Advanced Switch Capabilities
Non-blocking store-and-forward switch fabric assures
fast packet delivery by utilizing 1024-entry forwarding
table
64kb frame buffer RAM
IEEE 802.1q VLAN support for up to 128 active VLAN
groups (full-range 4096 of VLAN IDs)
IEEE 802.1p/q tag insertion or removal on a per port
basis (egress)
VLAN ID tag/untag options on per port basis
Fully compliant with IEEE 802.3/802.3u standards
IEEE 802.3x full-duplex with force mode option and half-
duplex back-pressure collision flow control
IEEE 802.1w rapid spanning tree protocol support
IGMP v1/v2/v3 snooping for multicast packet filtering
QoS/CoS packets prioritization support: 802.1p,
DiffServ-based and re-mapping of 802.1p priority field
per port basis on four priority levels
IPv4/IPv6 QoS support
IPv6 multicast listener discovery (MLD) snooping
Programmable rate limiting at the ingress and egress
ports on a per port basis
Jitter-free per-packet-based rate limiting support
Tail tagging mode (one byte added before FCS) support
on Port 5 to inform the processor which ingress port
receives the packet and its priority
Broadcast storm protection with percentage control
(global and per port basis)
1kb entry forwarding table with 64kb frame buffer
Four priority queues with dynamic packet mapping for
IEEE 802.1p, IPv4 ToS (DIFFSERV), IPv6 traffic class,
etc.
Supports wake-on-LAN (WoL) using AMD’s Magic
Packet™
VLAN and address filtering
Supports 802.1x port-based security, authentication,
and MAC-based authentication via access control lists
(ACL)
Provides port-based and rule-based ACLs to support
Layer 2 MAC SA/DA address, Layer 3 IP address and
IP mask, Layer 4 TCP/UDP port number, IP protocol,
TCP flag, and compensation for the port security filtering
Ingress and egress rate limit based on bit per second
(bps) and packet-based rate limiting (pps)
Configuration Registers Access
High speed (4-wire, up to 50MHz) interface (SPI) to
access all internal registers
MII management interface (MIIM, MDC/MDIO 2-wire) to
access all PHY registers per clause 22.2.4.5 of the IEEE
802.3 specification
July 23, 2014
2
Revision 1.0
 

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