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KSZ8765CLXCC View Datasheet(PDF) - Micrel

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KSZ8765CLXCC Datasheet PDF : 153 Pages
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Micrel, Inc.
KSZ8765CLX
List of Tables
Table 1. MDI/MDI-X Pin Definitions .................................................................................................................................... 21
Table 2. Internal Function Block Status .............................................................................................................................. 30
Table 3. Available Interfaces............................................................................................................................................... 35
Table 4. SPI Connections ................................................................................................................................................... 35
Table 5. MII Management Interface Frame Format ............................................................................................................ 38
Table 6. Signals of GMII/RGMII/MII/RMII ........................................................................................................................... 39
Table 7. Port 5 SW5-MII Connection .................................................................................................................................. 40
Table 8. Port 5 SW5-GMII Connection ............................................................................................................................... 41
Table 9. Port 5 SW5-RGMII Connection ............................................................................................................................. 41
Table 10. Port 5 SW5-RGMII Clock Delay Configuration with Connection Partner.............................................................. 42
Table 11. Port 5 SW5-RMII Connection(6)............................................................................................................................. 43
Table 12. Port Settings and Software Actions for Spanning Tree States ............................................................................. 45
Table 13. Port Settings and Software Actions for Rapid Spanning Tree States................................................................... 46
Table 14. Tail Tag Rules ....................................................................................................................................................... 47
Table 15. FID+DA Look-Up in the VLAN Mode .................................................................................................................... 49
Table 16. FID+SA Look-Up in the VLAN Mode .................................................................................................................... 49
Table 17. 10/100/1000Mbps Rate Selection for the Rate Limit ............................................................................................ 50
Table 18. Mapping of Functional Areas within the Address Space ...................................................................................... 58
Table 19. Format of Static MAC Addresses for Reads (32 Entries) ................................................................................... 102
Table 20. Format of Static MAC Addresses for Writes (32 Entries) ................................................................................... 103
Table 21. VLAN Table ......................................................................................................................................................... 104
Table 22. Indirect Registers and VLAN ID .......................................................................................................................... 106
Table 23. Dynamic MAC Address Table ............................................................................................................................. 107
Table 24. PME Indirect Registers ....................................................................................................................................... 109
Table 25. Temporary Storage for 14-Bytes ACL Rules ...................................................................................................... 112
Table 26. ACL Read and Write Control .............................................................................................................................. 120
Table 27. EEE Global Registers ......................................................................................................................................... 122
Table 28. EEE Port Registers ............................................................................................................................................. 123
Table 29. Port 1 MIB Counter Indirect Memory Offerts ...................................................................................................... 129
Table 30. Format of Per-Port MIB Counters ....................................................................................................................... 130
Table 31. All Port-Dropped Packet MIB Counters .............................................................................................................. 130
Table 32. Format of Per-Port Total RX/TX Bytes MIB Counters ........................................................................................ 131
Table 33. Format of All Port Dropped Packet MIB Counters .............................................................................................. 131
Table 34. GMII Timing Parameters ..................................................................................................................................... 140
Table 35. RGMII v2.0 Specification .................................................................................................................................... 141
Table 36. MAC Mode MII Timing Parameters..................................................................................................................... 142
Table 37. PHY Mode MII Timing Parameters ..................................................................................................................... 143
Table 38. RMII Timing Parameters ..................................................................................................................................... 144
Table 39. SPI Input Timing Parameters .............................................................................................................................. 145
Table 40. SPI Output Timing Parameters ........................................................................................................................... 146
Table 41. Auto-Negotiation Timing Parameters.................................................................................................................. 147
Table 42. MDC/MDIO Timing Parameters .......................................................................................................................... 148
Table 43. Reset Timing Parameters ................................................................................................................................... 149
Table 44. Transformer Selection Criteria ............................................................................................................................ 151
Table 45. Qualified Magnetic Vendors ................................................................................................................................ 151
Table 46. Typical Reference Crystal Characteristics .......................................................................................................... 151
July 23, 2014
10
Revision 1.0
 

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