M29F800FB5AN6E2 View Datasheet(PDF) - Micron Technology
Part Name
Description
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M29F800FB5AN6E2 Datasheet PDF : 55 Pages
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M29FxxxFT/B
Signal Descriptions
Signal Descriptions
The signal description table below is a comprehensive list of signals for this device fami-
ly. All signals listed may not be supported on this device. See Signal Assignments for in-
formation specific to this device.
Table 2: Signal Descriptions
Name
A[MAX:0]
CE#
OE#
WE#
BYTE#
RST#
DQ[7:0]
DQ[14:8]
DQ15/A-1
RY/BY#
Type
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
Output
Description
Address: Selects the cells in the array to access during READ operations. During WRITE oper-
ations, they control the commands sent to the command interface of the program/erase con-
troller.
Chip enable: Activates the device, enabling READ and WRITE operations to be performed.
When CE# is HIGH, all other pins are ignored.
Output enable: Controls the bus READ operation.
Write enable: Controls the bus WRITE operation of the command interface.
Byte/word organization select: Switches between x8 and x16 bus modes. When BYTE# is
LOW, the device is in x8 mode; when HIGH, the device is in x16 mode.
Reset: Applies a hardware reset to the device, which is achieved by holding RST# LOW for at
least tPLPX. After RST# goes HIGH, the device is ready for READ and WRITE operations (after
tPHEL or tRHEL, whichever occurs last).
Holding RST# at VID will temporarily unprotect the protected blocks. PROGRAM and ERASE
operations on all blocks will then be possible. The transition from VIH to VID must be slower
than tPHPHH.
Data I/O: Outputs the data stored at the selected address during a READ operation. During
WRITE operations, they represent the commands sent to the command interface of the pro-
gram/erase controller.
Data I/O: Outputs the data stored at the selected address during a READ operation when
BYTE# is HIGH. When BYTE# is LOW, these pins are not used and are High-Z. During WRITE
operations, these bits are not used. When reading the status register, these bits should be ig-
nored.
Data I/O or address input: When the device operates in x16 bus mode, this pin behaves as
data I/O, together with DQ[14:8]. When the device operates in x8 bus mode, this pin behaves
as the least significant bit of the address.
Except where stated explicitly otherwise, DQ15 = data I/O (x16 mode); A-1 = address input (x8
mode).
Ready busy: Open-drain output that can be used to identify when the device is performing
a PROGRAM or ERASE operation. During PROGRAM or ERASE operations, RY/BY# is LOW,
and is High-Z during read mode, auto select mode, and erase suspend mode. After a hard-
ware reset, READ and WRITE operations cannot begin until RY/BY# goes High-Z (see RESET
AC Specifications for more details).
The use of an open-drain output enables the RY/BY# pins from several devices to be connec-
ted to a single pull-up resistor to VCCQ. A low value will then indicate that one (or more) of
the devices is (are) busy.
PDF: 09005aef845656da
m29fxxxf/t_2mb-16mb.pdf - Rev. B 2/14 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
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