CMX882 View Datasheet(PDF) - CML Microcircuits
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CMX882 Datasheet PDF : 70 Pages
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FRS Signalling Processor
CMX882
1.6.20 $C8 PROGRAMMING REGISTER: 16-bit write-only
Bit: 15
14
13 12 11 10 9 8 7 6 5 4 3 2 1 0
First Block Block Num.
Word Num. or Data
Programming Data
This register is used for programming various gains, levels, offset compensations, tones and codes. If
the user programs any of these values then bit 4 of $C0 (Power Down Control) must be set to '1'.
Following a C-BUS Reset or a Power Up Reset, the programmed values are initialised in accordance with
the settings described in section 1.6.2 (C-BUS Reset).
The Signal Processing function and the XTAL clock circuit must both be enabled in order to write to the
Programming Register, so Power Down Control register bit 5 must be set to '1' and bit 3 must be set to
'0'.
The Programming Register should only be written to when the Programming Flag bit (bit 0) of the Status
register is set to '1' and the Rx and Tx modes are disabled (bits 0 and 1 of the Mode Control register both
'0'). The Programming Flag is cleared when the Programming Register is written to. When the
corresponding programming action has been completed (normally within 250µs) the CMX882 will set the
flag back to '1' to indicate that it is now safe to write the next programming value. The Programming
Register must not be written to while the Programming Flag bit is '0'. Programming is done by writing a
sequence of 16-bit words to the Programming Register, in the order shown in the following tables.
Writing data to the Programming Register must be performed in the order shown for each of the blocks,
however the order in which the blocks are written is not critical. If later words in a block do not require
updating the user may stop programming that block when the last change has been performed. e.g. If
only 'Fine output gain 1' needs to be changed the host will need to write to P4.0, P4.1 and P4.2 only.
The user must not exceed the defined word counts for each block. The word P4.8 is allocated for
production testing and must not be accessed in normal operation.
The high order bits of each word define which block the word belongs to, and if it is the first word of that
block:
Bit 15
1
0
X
X
X
X
X
Bit 14
X
X
1
1
1
1
0
Bit 13 Bit 12
Bit 11 – Bit 0
X
X 1st data for each block
X
X 2nd and following data
0
0 Write to block 0 (12 bit words)
0
1 Write to block 1 (12 bit words)
1
0 Write to block 2 (12 bit words)
1
1 Reserved - do not use
Write to block 4 (14 bit words)
Block 0 – Modem Configuration:
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P0.0 1 1 0 0
0
MSK Frame Sync LSB
P0.1 0 1 0 0
0
MSK Frame Sync MSB
P0.2 0 1 0 0
0
Scramble Seed 1 LSB
P0.3 0 1 0 0
0
Scramble Seed 1 MSB
P0.4 0 1 0 0
0
Scramble Seed 2 LSB
P0.5 0 1 0 0
0
Scramble Seed 2 MSB
P0.6 0 1 0 0
0
MSK Bit Sync LSB
P0.7 0 1 0 0
0
MSK Bit Sync MSB
2004 CML Microsystems Plc
50
D/882/7
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