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BR34L02FV-W View Datasheet(PDF) - ROHM Semiconductor
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Description
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BR34L02FV-W
256×8 bit Electrically Erasable PROM (based on Serial Presence Detect)
ROHM Semiconductor
BR34L02FV-W Datasheet PDF : 25 Pages
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Memory ICs
z
Synchronous data timing
SCL
SDA
(IN)
SDA
(OUT)
t
HD :
STA
t
BUF
BR34L02FV-W
t
R
t
F
t
HIGH
t
SU
: DAT
t
LOW
t
HD
: DAT
t
PD
t
DH
SCL
SDA
t
SU
: STA
t
HD
: STA
t
SU
: STO
START BIT
Fig.8 SYNCHRONOUS DATA TIMING
•
SDA data is latched into the chip at the rising edge of SCL clock.
•
Output data toggles at the falling edge of SCL clock.
z
Write cycle timing
SCL
STOP BIT
SDA
D0
WRITE DATA (n)
ACK
t
WR
STOP CONDITION
START CONDITION
Fig.9 WRITE CYCLE TIMING
Rev.A
6/24
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