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STA559BW View Datasheet(PDF) - STMicroelectronics

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Description
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STA559BW Datasheet PDF : 67 Pages
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STA559BW
Contents
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
Configuration registers (addr 0x00 to 0x05) . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1.6 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . . 40
6.2.1 Mute/line output configuration register (addr 0x06) . . . . . . . . . . . . . . . . 41
6.2.2 Master volume register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.2.3 Channel 1 volume (addr 0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.2.4 Channel 2 volume (addr 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.2.5 Channel 3 / line output volume (addr 0x0A) . . . . . . . . . . . . . . . . . . . . . 42
Audio preset registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . 43
6.3.1 Audio preset register 1 (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.3.2 Audio preset register 2 (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . . 45
Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 47
6.6.1 Limiter 1 attack/release rate (addr 0x12) . . . . . . . . . . . . . . . . . . . . . . . . 47
6.6.2 Limiter 1 attack/release threshold (addr 0x13) . . . . . . . . . . . . . . . . . . . 47
6.6.3 Limiter 2 attack/release rate (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . . 48
6.6.4 Limiter 2 attack/release threshold (addr 0x15) . . . . . . . . . . . . . . . . . . . 48
6.6.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 52
6.7.1 Coefficient address register (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . . 52
6.7.2 Coefficient b1 data register bits (addr 0x17 - 0x19) . . . . . . . . . . . . . . . . 53
6.7.3 Coefficient b2 data register bits (addr 0x1A - 0x1C) . . . . . . . . . . . . . . . 53
6.7.4 Coefficient a1 data register bits (addr 0x1D - 0x1F) . . . . . . . . . . . . . . . 53
6.7.5 Coefficient a2 data register bits (addr 0x20 - 0x22) . . . . . . . . . . . . . . . . 53
6.7.6 Coefficient b0 data register bits (addr 0x23 - 0x25) . . . . . . . . . . . . . . . . 54
6.7.7 Coefficient read/write control register (addr 0x26) . . . . . . . . . . . . . . . . . 54
6.7.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 59
Distortion compensation registers (addr 0x29 - 0x2A) . . . . . . . . . . . . . . . 59
Fault detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . . 59
DocID18190 Rev 2
3/67
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