STA559BW
Register description
Invalid input detect mute enable
Bit R/W
2
R/W
Table 44. Invalid input detect mute enable
RST
Name
Description
1
IDE
0: disables the automatic invalid input detect mute
1: enables the automatic invalid input detect mute
Setting the IDE bit enables this function, which looks at the input I²S data and automatically
mutes if the signals are perceived as invalid.
Binary output mode clock loss detection
Bit R/W
3
R/W
Table 45. Binary output mode clock loss detection
RST
Name
Description
1
BCLE
0: binary output mode clock loss detection disabled
1: binary output mode clock loss detection enable
Detects loss of input MCLK in binary mode and will output 50% duty cycle.
LRCK double trigger protection
Bit R/W
4
R/W
Table 46. LRCK double trigger protection
RST
Name
Description
1
LDTE
0: LRCLK double trigger protection disabled
1: LRCLK double trigger protection enabled
LDTE, when enabled, prevents double trigger of LRCLK on instable I²S input.
Auto EAPD on clock loss
Bit R/W
5
R/W
Table 47. Auto EAPD on clock loss
RST
Name
Description
0
ECLE
0: auto EAPD on clock loss not enabled
1: auto EAPD on clock loss
When active, issues a power device power down signal (EAPD) on clock loss detection.
IC power down
Bit R/W
6
R/W
Table 48. IC power down
RST
Name
Description
1
PWDN
0: IC power down low-power condition
1: IC normal operation
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