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DS2482X-101-U View Datasheet(PDF) - Maxim Integrated

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DS2482X-101-U
MaximIC
Maxim Integrated MaximIC
DS2482X-101-U Datasheet PDF : 24 Pages
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Single-Channel 1-Wire Master with Sleep Mode
SDA
tBUF
tLOW
SCL
tHD:STA
STOP
START
tR
tHD:DAT
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 9. I2C Timing Diagram
tF
tHIGH
tSU:DAT
I2C Definitions
The following terminology is commonly used to
describe I2C data transfers. The timing references are
defined in Figure 9.
Bus Idle or Not Busy: Both SDA and SCL are inac-
tive and in their logic-high states.
START Condition: To initiate communication with a
slave, the master must generate a START condition.
A START condition is defined as a change in state of
SDA from high to low while SCL remains high.
STOP Condition: To end communication with a
slave, the master must generate a STOP condition. A
STOP condition is defined as a change in state of
SDA from low to high while SCL remains high.
Repeated START Condition: Repeated STARTs are
commonly used for read accesses to select a spe-
cific data source or address to read from. The mas-
ter can use a repeated START condition at the end
of a data transfer to immediately initiate a new data
transfer following the current one. A repeated START
condition is generated the same way as a normal
START condition, but without leaving the bus idle
after a STOP condition.
Data Valid: With the exception of the START and
STOP condition, transitions of SDA can occur only
during the low state of SCL. The data on SDA must
remain valid and unchanged during the entire high
pulse of SCL plus the required setup and hold time
(tHD:DAT after the falling edge of SCL and tSU:DAT
tHD:STA
tSP
tSU:STA
REPEATED
START
SPIKE
SUPPRESSION
tSU:STO
before the rising edge of SCL; see Figure 9). There
is one clock pulse per bit of data. Data is shifted into
the receiving device during the rising edge of SCL.
When finished with writing, the master must release
the SDA line for a sufficient amount of setup time
(minimum tSU:DAT + tR in Figure 9) before the next
rising edge of SCL to start reading. The slave shifts
out each data bit on SDA at the falling edge of the
previous SCL pulse and the data bit is valid at the
rising edge of the current SCL pulse. The master
generates all SCL clock pulses, including those
needed to read from a slave.
Acknowledge: Typically a receiving device, when
addressed, is obliged to generate an acknowledge
after the receipt of each byte. The master must gen-
erate a clock pulse that is associated with this
acknowledge bit. A device that acknowledges must
pull SDA low during the acknowledge clock pulse in
such a way that SDA is stable low during the high
period of the acknowledge-related clock pulse plus
the required setup and hold time (tHD:DAT after the
falling edge of SCL and tSU:DAT before the rising
edge of SCL).
Not Acknowledged by Slave: A slave device may
be unable to receive or transmit data, for example,
because it is busy performing some real-time func-
tion or is in sleep mode. In this case, the slave
device does not acknowledge its slave address and
leaves the SDA line high. A slave device that is
ready to communicate acknowledges at least its
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