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R5F21142SP-U0 View Datasheet(PDF) - Renesas Electronics

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R5F21142SP-U0 Datasheet PDF : 277 Pages
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R8C/14 Group, R8C/15 Group
9. Clock Generation Circuit
CM10=1(Stop Mode)
SQ
RESET
Power-on reset
Software reset
Interrupt request
R
SQ
WAIT
R
Instruction
CM13
XIN
XOUT
HRA1 Register
Frequency Adjustable
HRA2 Register
On-Chip Oscillator Clock
HRA00
High-Speed
On-Chip
Oscillator
fRING-fast
HRA01=1
HRA01=0
fRING
fRING128
1/128
Timer C
INT0
CM14
Low-Speed
On-Chip
Oscillator
fRING-S
Power-On
Reset Circuit
Voltage
Detection
Circuit
b
f1
Main Clock
Oscillation
Stop
Detection
OCD2=1
c
f2
d
f4
e
f8
g
f32
Watchdog
Timer
SSU
Timer X
Timer Z
A/D
Converter
UART0
OCD2=0
a
Divider
h
CPU Clock
CM05
CM13
CM02
System Clock
b
c
d
a
1/2
1/2
1/2
e
1/2
g
1/2
CM02, CM05, CM06: Bits in CM0 register
CM10, CM13, CM14, CM16, CM17: Bits in CM1 register
OCD0, OCD1, OCD2: Bits in OCD register
HRA00, HRA01: Bits in HRA0 register
CM06=1
CM06=0
CM17 to CM16=10b
CM06=0
CM17 to CM16=01b
CM06=0
CM17 to CM16=00b
CM06=0
CM17 to CM16=11b
h
Oscillation Stop Detection Circuit
Details of Divider
Forcible discharge when OCD0(1)=0
Main Clock
Pulse generation
circuit for clock
edge detection and
charge, discharge
control circuit
Charge,
Discharge
Circuit
OCD1(1)
NOTES :
1. Set the same value to the OCD1 and OCD0 bits.
Oscillation Stop Detection
Interrupt Generation
Circuit Detection
Watchdog
Timer Interrupt
Voltage Watch
2 Interrupt
OCD2 Bit Switch Signal
CM14 Bit Switch Signal
Oscillation Stop
Detection,
Watchdog Timer,
Voltage Monitor 2
Interrupt
Figure 9.1 Clock Generation Circuit
Rev.2.10 Jan 19, 2006 Page 39 of 253
REJ09B0164-0210
 

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