R8C/14 Group, R8C/15 Group
7. Processor Mode
Processor Mode Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
PM1
Address
0005h
After Reset
00h
Bit Symbol
Bit Name
Function
RW
—
Nothing is assigned. When w rite, set to “0”.
(b0) When read, its content is indeterminate.
—
—
Reserved Bit
Set to “0”
(b1)
RW
WDT Interrupt/Reset Sw itch Bit
0 : Watchdog Timer Interrupt
PM12
1 : Watchdog Timer Reset(2)
RW
—
Nothing is assigned. When w rite, set to “0”.
(b6-b3) When read, its content is “0”.
—
—
Reserved Bit
Set to “0”
(b7)
RW
NOTES :
1. Set the PRC1 bit in the PRCR register to “1” (w rite enable) before rew riting to this register.
2. The PM12 bit is set to “1” by a program (It remains unchanged even if it is set to “0”).
When the CSPRO bit in the CSPR register is set to “1” (selects count source protect mode), the PM12 bit is
automatically set to “1”.
Figure 7.2 PM1 Register
Rev.2.10 Jan 19, 2006 Page 36 of 253
REJ09B0164-0210