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R5F21143DSP View Datasheet(PDF) - Renesas Electronics

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R5F21143DSP Datasheet PDF : 277 Pages
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R8C/14 Group, R8C/15 Group
6. Voltage Detection Circuit
Voltage Monitor 1 Circuit Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
VW1C
Address
0036h
Bit Symbol
Bit Name
Voltage Monitor 1 Reset Enable
VW1C0 Bit(3)
Voltage Monitor 1 Digital Filter
Disable Mode Select Bit
VW1C1
Reserved Bit
VW1C2
After Reset(2)
Hardw are Reset : 0000X000b
Pow er-On Reset, Voltage Monitor 1 Reset :
0100X001b
Function
RW
0 : Disable
1 : Enable
RW
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled mode
RW
(digital filter circuit disabled)
Set to “0”.
RW
(b3)
VW1F0
Reserved Bit
Sampling Clock Select Bit
VW1F1
When read, its content is indeterminate.
RO
b5 b4
0 0 : fRING-S divide-by-1
RW
0 1 : fRING-S divide-by-2
1 0 : fRING-S divide-by-4
1 1 : fRING-S divide-by-8
RW
Voltage Monitor 1 Circuit Mode When the VW1C0 bit is set to “1” (enables
VW1C6 Select Bit
voltage monitor 1 reset), set to “1”.
RW
Voltage Monitor 1 Reset
VW1C7 Generation Condition Select Bit
When the VW1C1 bit is set to “1” (digital filter
disabled mode), set to “1”.
RW
NOTES :
1. Set the PRC3 bit in the PRCR register to “1” (w rite enable) before w riting to this register.
When rew riting the VW1C register, the VW1C2 bit may be set to “1”. Set the VW1C2 bit to “0” after rew riting the
VW1C register.
2. The value after reset remains unchanged in softw are reset, w atchdogi timer reset and voltage monitor 2 reset.
3. The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to “1” (voltage detection 1 circuit
enabled). Set the VW1C0 bit to “0” (disable), w hen the VCA26 bit is set to “0” (voltage detection 1 circuit disabled).
Figure 6.5 VW1C Register
Rev.2.10 Jan 19, 2006 Page 29 of 253
REJ09B0164-0210
 

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