AD9144BCPAZRL View Datasheet(PDF) - Analog Devices

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Description

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AD9144BCPAZRL

Quad, 16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter

Analog Devices 

Data Sheet

Across power cycles, links, and devices

• MinDelay is the minimum of all Delay measurements

• MaxDelay is the maximum of all Delay measurements

For safety, a guard band of 1 PClock cycle is added to each end

of the link delay and calculate LMFCVar and LMFCDel with

the following equation:

LMFCVar = (MaxDelay + 1) − (MinDelay − 1)

Note that if LMFCVar must be more than 10, the AD9144 is

unable to tolerate the variable delay in the system.

For Subclass 1

LMFCDel = ((MinDelay − 1) × PClockFactor) % K

For Subclass 0

LMFCDel = (MinDelay − 1) % PClockPerMF

Program the same LMFCDel and LMFCVar across all links and

devices.

See the Link Delay Setup Example, Without Known Delay

section for an example calculation.

AD9144

CROSSBAR SETUP

Register 0x308 to Register 0x30B allow arbitrary mapping of

physical lanes (SERDINx±) to logical lanes used by the SERDES

deframers.

Table 34. Crossbar Registers

Address Bits

Logical Lane

0x308 [2:0]

LOGICAL_LANE0_SRC

0x308 [5:3]

LOGICAL_LANE1_SRC

0x309 [2:0]

LOGICAL_LANE2_SRC

0x309 [5:3]

LOGICAL_LANE3_SRC

0x30A [2:0]

LOGICAL_LANE4_SRC

0x30A [5:3]

LOGICAL_LANE5_SRC

0x30B [2:0]

LOGICAL_LANE6_SRC

0x30B [5:3]

LOGICAL_LANE7_SRC

Write each LOGICAL_LANEy_SRC with the number (x) of the

desired physical lane (SERDINx±) from which to obtain data.

By default, all logical lanes use the corresponding physical lane as

their data source. For example, by default LOGICAL_LANE0_

SRC = 0, meaning that Logical Lane 0 receives data from

Physical Lane 0 (SERDIN0±). If instead the user wants to use

SERDIN4± as the source for Logical Lane 0, the user must write

LOGICAL_LANE0_SRC = 4.

Rev. B | Page 33 of 125

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