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AD9144BCPAZRL View Datasheet(PDF) - Analog Devices

Part Name
Description
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AD9144BCPAZRL Datasheet PDF : 125 Pages
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Data Sheet
AD9144
Pin No.
20
21
22
23
24
25
26
Mnemonic
SVDD12
VTT
SVDD12
SYNCOUT0+
SYNCOUT0−
VTT
SERDIN2+
27
SERDIN2−
28
SVDD12
29
SERDIN3+
30
SERDIN3−
31
SVDD12
32
SVDD12
33
SVDD12
34
LDO_BYP1
35
SIOVDD33
36
SVDD12
37
SERDIN4−
38
SERDIN4+
39
SVDD12
40
SERDIN5−
41
SERDIN5+
42
VTT
43
SYNCOUT1−
44
SYNCOUT1+
45
SVDD12
46
VTT
47
SVDD12
48
SERDIN6−
49
SERDIN6+
50
SVDD12
51
SERDIN7−
52
SERDIN7+
53
DVDD12
54
GND
55
GND
56
PVDD12
57
PVDD12
58
PROTECT_OUT1
59
PROTECT_OUT0
60
IRQ
61
RESET
Description
1.2 V JESD204B Receiver Supply.
1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins.
1.2 V JESD204B Receiver Supply.
Positive LVDS Sync (Active Low) Output Signal Channel Link 0.
Negative LVDS Sync (Active Low) Output Signal Channel Link 0.
1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins.
Serial Channel Input 2, Positive. CML compliant. SERDIN2+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 2, Negative. CML compliant. SERDIN2− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 3, Positive. CML compliant. SERDIN3+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 3, Negative. CML compliant. SERDIN3− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supply.
1.2 V JESD204B Receiver Supply.
1.2 V JESD204B Receiver Supply.
LDO SERDES Bypass. This pin requires a 1 Ω resistor in series with a 1 µF capacitor to ground.
3.3 V Supply for SERDES.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 4, Negative. CML compliant. SERDIN4− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 4, Positive. CML compliant. SERDIN4+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 5, Negative. CML compliant. SERDIN5− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 5, Positive. CML compliant. SERDIN5+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins.
Negative LVDS Sync (Active Low) Output Signal Channel Link 1.
Positive LVDS Sync (Active Low) Output Signal Channel Link 1.
1.2 V JESD204B Receiver Supply.
1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 6, Negative. CML compliant. SERDIN6− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 6, Positive. CML compliant. SERDIN6+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 7, Negative. CML compliant. SERDIN7− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 7, Positive. CML compliant. SERDIN7+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V Digital Supply.
Ground. Connect GND to the ground plane.
Ground. Connect GND to the ground plane.
1.2 V Supply. PVDD12 provides a clean supply.
1.2 V Supply. PVDD12 provides a clean supply.
Power Detection Protection Pin Output for DAC2 and DAC3. Pin 58 is high when power protection is in process.
Power Detection Protection Pin Output for DAC0 and DAC1. Pin 59 is high when power protection is in process.
Interrupt Request (Active Low, Open Drain).
Reset. This pin is active low. CMOS levels are determined with respect to IOVDD.
Rev. B | Page 13 of 125
 

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