T8502 and T8503 Dual PCM Codecs with Filters
Two channels of PCM data input and output are passed
through only two ports, DX and DR, so some type of
time-slot assignment is necessary. The scheme used
here is to utilize a ﬁxed-data rate mode of 32 or 64 time
slots corresponding to master clock frequencies of
either 2.048 MHz or 4.096 MHz, respectively. Each
device has four frame sync (FSX and FSR) inputs, one
pair for each channel. During a single 125 µs frame,
each frame sync input is supplied a single pulse. The
timing of the respective frame sync pulse indicates the
beginning of the time slot during which the data for that
channel is clocked in or out of the device. FSX and FSR
must be high for a minimum of one master clock cycle.
They can be operated independently, or they can be
tied together for coincident transmit and receive data
transfer. During a frame, channel 0 and 1 transmit
frame sync pulses must be separated from each other
by one or more time slots. Likewise, channel 0 and 1
receive frame sync pulses must be separated from
each other by one or more time slots. Both transmit and
receive frame strobes must be derived from master
clock, but they do not need to be byte aligned.
A channel is placed in standby mode by removing both
FSX and FSR for 500 µs. Note, if any one of those
pulses (per channel) is removed, operation is indeter-
minate. Standby mode reduces overall device power
consumption by turning off nonessential circuitry. Criti-
cal circuits that ensure a fast, quiet powerup are kept
active. Master clock need not be active when both
channels are in standby mode.
The frequency of the master clock must be either
2.048 MHz or 4.096 MHz. Internal circuitry determines
the master clock frequency during the powerup reset
The analog input section in Figure 2 includes an on-
chip op amp that is used in conjunction with external,
user-supplied resistors to vary encoder passband gain.
The feedback resistance (RF) should range from 10 kΩ
to 200 kΩ, and capacitance from GSX to ground should
be kept to less than 50 pF. The input signal at VFXIN
should be ac coupled. For best performance, the maxi-
mum gain of this op amp should be limited to 20 dB or
less. Gain in the receive path is selectable via the GS
pins as either 0 dB or –3.5 dB.
Figure 2. Typical Analog Input Section
Figure 3. Pin Diagram
Lucent Technologies Inc.