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MC14013BFR2 View Datasheet(PDF) - ON Semiconductor

Part Name
Description
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MC14013BFR2
ON-Semiconductor
ON Semiconductor ON-Semiconductor
MC14013BFR2 Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
MC14013B
Dual Type D Flip-Flop
The MC14013B dual type D flipflop is constructed with MOS
Pchannel and Nchannel enhancement mode devices in a single
monolithic structure. Each flipflop has independent Data, (D), Direct
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary
outputs (Q and Q). These devices may be used as shift register
elements or as type T flipflops for counter and toggle applications.
Features
Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic EdgeClocked FlipFlop Design
Logic state is retained indefinitely with clock level either high or
low; information is transferred to the output only on the
positivegoing edge of the clock pulse
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range
PinforPin Replacement for CD4013B
These Devices are PbFree, Halogen Free and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
0.5 to +18.0
V
0.5 to VDD + 0.5
V
Iin, Iout Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
55 to +125
°C
Tstg Storage Temperature Range
65 to +150
°C
TL
Lead Temperature
(8Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP14
P SUFFIX
CASE 646
MARKING
DIAGRAMS
14
MC14013BCP
AWLYYWWG
1
14
SOIC14
D SUFFIX
CASE 751A
14013BG
AWLYWW
1
TSSOP14
DT SUFFIX
CASE 948G
14
14
013B
ALYW G
G
1
SOEIAJ14
F SUFFIX
CASE 965
14
MC14013B
ALYWG
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = PbFree Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
1
September, 2012 Rev. 9
Publication Order Number:
MC14013B/D
 

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