29F64G08CBAAA View Datasheet(PDF) - Micron Technology

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Description

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29F64G08CBAAA

NAND Flash Memory

Micron Technology 

Micron Confidential and Proprietary

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

Bus Operation – Synchronous Interface

Figure 32: Synchronous Address Cycle

CE#

CLE

ALE

CLK

W/R#

DQS

DQ[7:0]

tCS

tCH

tCALS

tCALS

tCKL tCKH

tCAD

tCALH

tCALS tCALH

tCALS tCALH

tCK

tCALS

tDQSHZ

tCAD starts here1

tCALH

tCAS tCAH

ADDRESS

Undefined

Don’t Care

Note: 1. When CE# remains LOW, tCAD begins at the rising edge of the clock from which the

command cycle is latched for subsequent command, address, data input, or data output

cycle(s).

Synchronous DDR Data Input

To enter the DDR data input mode, the following conditions must be met:

• CLK is running

• CE# is LOW

• W/R# is HIGH

• tCAD is met

• DQS is LOW

• ALE and CLE are HIGH on the rising edge of CLK

Upon entering the DDR data input mode after tDQSS, data is written from DQ[7:0] to

the cache register on each and every rising and falling edge of DQS (center-aligned)

when CLK is running and the DQS to CLK skew meets tDSH and tDSS, CE# is LOW,

W/R# is HIGH, and ALE and CLE are HIGH on the rising edge of CLK.

To exit DDR data input mode, the following conditions must be met:

• CLK is running and the DQS to CLK skew meets tDSH and tDSS

• CE# is LOW

• W/R# is HIGH

PDF: 09005aef83d2277a

Rev. A 11/09 EN

42

Micron Technology, Inc. reserves the right to change products or specifications without notice.

©2009 Micron Technology, Inc. All rights reserved.

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