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29F64G08CBAAA View Datasheet(PDF) - Micron Technology

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29F64G08CBAAA
Micron
Micron Technology Micron
29F64G08CBAAA Datasheet PDF : 159 Pages
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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Bus Operation – Synchronous Interface
Figure 31: Synchronous Command Cycle
CE#
CLE
ALE
CLK
W/R#
DQS
DQ[7:0]
tCS
tCH
tCALS
tCALS
tCAD
tCKL tCKH
tCALS tCALH
tCALS tCALH
tCALH
tCK
tCALS
tDQSHZ
tCAD starts here1
tCALH
tCAS tCAH
COMMAND
Undefined
Don’t Care
Note: 1. When CE# remains LOW, tCAD begins at the rising edge of the clock from which the
command cycle is latched for subsequent command, address, data input, or data output
cycle(s).
Synchronous Addresses
A synchronous address is written from DQ[7:0] to the address register on the rising edge
of CLK when CE# is LOW, ALE is HIGH, CLE is LOW, and W/R# is HIGH.
After an address is latched—and prior to issuing the next command, address, or data I/O
—the bus must go to bus idle mode on the next rising edge of CLK, except when the
clock period, tCK, is greater than tCAD.
Bits not part of the address space must be LOW (see Device and Array Organization).
The number of address cycles required for each command varies. Refer to the com-
mand descriptions to determine addressing requirements.
Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
addresses such as address cycles that follow the READ STATUS ENHANCED (78h) com-
mand, are accepted by die (LUNs), even when they are busy.
PDF: 09005aef83d2277a
Rev. A 11/09 EN
41
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009 Micron Technology, Inc. All rights reserved.
 

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