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29F128G08CEAAA View Datasheet(PDF) - Micron Technology

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29F128G08CEAAA
Micron
Micron Technology Micron
29F128G08CEAAA Datasheet PDF : 159 Pages
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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Bus Operation – Synchronous Interface
5. During data output from the NAND Flash device, DQS is an output generated from CLK
after tDQSCK delay.
6. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH
or VIL.
Synchronous Enable/Standby
In addition to the description in the section Asynchronous Enable/Standby (page 28),
the following requirements also apply when the synchronous interface is active.
Before enabling a target, CLK must be running and ALE and CLE must be LOW. When
CE# is driven LOW, all of the signals for the selected target are enabled. The target is not
enabled until tCS completes; the target's bus is then idle.
Prior to disabling a target, the target's bus must be idle. A target is disabled when CE# is
driven HIGH, even when it is busy. All of the target's signals are disabled except CE#,
WP#, and R/B#. After the target is disabled, CLK can be stopped.
A target enters low-power standby when it is disabled and is not busy. If the target is
busy when it is disabled, the target enters standby after all of the die (LUNs) complete
their operations.
Synchronous Bus Idle/Driving
A target's bus is idle or driving when CLK is running, CE# is LOW, ALE is LOW, and CLE
is LOW.
The bus is idle when W/R# transitions HIGH and is latched by CLK. During the bus idle
mode, all signals are enabled; DQS and DQ[7:0] are inputs. No commands, addresses,
or data are latched into the target; no data is output. When entering the bus idle mode,
the host must wait a minimum of tCAD before changing the bus mode. In the bus idle
mode, the only valid bus modes supported are: bus driving, command, address, and
DDR data input.
The bus is driving when W/R# transitions LOW and is latched by CLK. During the bus
driving mode, all signals are enabled; DQS is LOW and DQ[7:0] is driven LOW or HIGH,
but no valid data is output. Following the bus driving mode, the only valid bus modes
supported are bus idle and DDR data output.
PDF: 09005aef83d2277a
Rev. A 11/09 EN
39
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009 Micron Technology, Inc. All rights reserved.
 

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