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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Bus Operation – Asynchronous Interface
Asynchronous Data Input
Data is written from DQ[7:0] to the cache register of the selected die (LUN) on the rising
edge of WE# when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH.
Data input is ignored by die (LUNs) that are not selected or are busy (RDY = 0).
Figure 21: Asynchronous Data Input Cycles
CLE
CE#
ALE
WE#
DQx
tCLH
tALS
tWC
tWP
tWP
tWH
tDS tDH
Din M
tDS tDH
Din M+1
tCH
tWP
tDS tDH
Din N
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PDF: 09005aef83d2277a
Rev. A 11/09 EN
31
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