Q6275K791 View Datasheet(PDF) - Infineon Technologies

Part Name

Description

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Q6275K791

Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver with Digital Baseband Processing

Infineon Technologies 

TDA523x

Functional Description

Dual: ARFPLL1 and BRFPLL1:Conf.A RF PLL setting, channel 1 (Slave Mode &

Self Polling Mode)

ADDR: 0x22 and 0x43

Bit R/W Description

4:2 W RFPLLR1: Channel 1, PLL divider factor R1)

1:0 W RFPLLS1: Channel 1, PLL divider factor S1)

1)

Reset Value: 0x29

Dual: ARFPLL2 and BRFPLL2:Conf. ARF PLL setting, channel 2 (Self Polling

Mode)

ADDR: 0x23 and 0x44

Bit R/W Description

4:2 W RFPLLR2: Channel 2, PLL divider factor R1)

1:0 W RFPLLS2: Channel 2, PLL divider factor S1)

Reset Value: 0x08

Dual: ARFPLL3 and BRFPLL3:Conf.A RF PLL setting, channel 3 (Self Polling

Mode)

ADDR: 0x24 and 0x45

Bit R/W Description

4:2 W RFPLLR3: Channel 3, PLL divider factor R1)

1:0 W RFPLLS3: Channel 3, PLL divider factor S1)

Reset Value: 0x0A

1) Channels with receive frequencies close to harmonics of the reference crystal-frequency should not be used

in applications.

RFPLLAC: RF PLL Actual Channel Register

ADDR: 0x06

Reset Value: 0x00

Bit R/W Description

1:0 R RFPLLACS: Actual Channel

This Register is set after a Wake Up found in the Self Polling Mode

00b: No Channel was actually found

01b: Channel 1 Wake Up according to RFPLL1 setting was found

10b: Channel 2 Wake Up according to RFPLL2 setting was found

11b: Channel 3 Wake Up according to RFPLL3 setting was found

Data Sheet

45

Version 4.0, 2007-06-01

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