Q6275K791 View Datasheet(PDF) - Infineon Technologies

Part Name

Description

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Q6275K791

Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver with Digital Baseband Processing

Infineon Technologies 

TDA523x

Functional Description

CMC0: Chip Mode Control Register 0

ADDR: 0x02

Reset Value: 0x40

Bit R/W Description

2 W DCE: Dual Configuration Enable

This Bit is relevant only in Self Polling Mode. It defines whether both

configurations are used.

0: Only Config A is used

1: First Config A is used; then Config B is used

RFPLLAC: RF PLL Actual Channel Register

ADDR: 0x06

Reset Value: 0x00

Bit R/W Description

1:0 R RFPLLACS: Actual Channel

This register is set after a Wake Up found in the Self Polling Mode

00b: No channel was actually found

01b: Channel 1 according to RFPLL1 setting was found

10b: Channel 2 according to RFPLL2 setting was found

11b: Channel 3 according to RFPLL3 setting was found

Dual: AMT and BMT: Conf.A Modulation Type Register

ADDR: 0x21 and 0x42

Reset Value: 0x04

Bit R/W Description

3:2 W NOC: Number of channels

Only used in the Self Polling Mode to define how many channels have to be

scanned. In the Slave Mode there is only 1 channel used, whatever here is

configured.

Min: 01b = 1 channel

Max: 11b= 3 channels

The following state diagrams and explanations help to illustrate the behavior during Self

Polling Mode. First, there is a wake up search for a wake up pattern according

configuration A on up to three different channels. Then, there is an optional search for a

wake up pattern according configuration B, again including up to 3 channels.

In applications using only a single configuration, settings are always taken from

Configuration A

Data Sheet

40

Version 4.0, 2007-06-01

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