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Q6275K791 View Datasheet(PDF) - Infineon Technologies

Part NameDescriptionManufacturer
Q6275K791 Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver with Digital Baseband Processing Infineon
Infineon Technologies Infineon
Q6275K791 Datasheet PDF : 186 Pages
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TDA523x
Functional Description
2.4.4 RF-PLL Synthesizer
The Phase Locked Loop RF synthesizer consists of a VCO, programmable divider
chains, a phase detector, a charge pump and a loop filter. The on chip VCO includes a
spiral-inductor and varactors. The loop filter is also fully integrated on chip. The VCO
signal is fed to both the programmable synthesizer divider chain and to a programmable
RF divider. This RF divider allows selection between three operational frequency bands
and drives a fixed divider by four, which generates the quadrature LO signals for the
Image Reject Mixer.
LO-Signals
I
Q
0 ° 90 °
Divide by 4
Divide by A
A = 3 for 302..320 MHz
A = 2 for 433..450 MHz
2
A = 1 for 865..870 MHz
RFPLLA
2
3
S = -1, 0, +1
R = 1 ... 8
Divide by N = 256 * R + S
RF-VCO
Loop-
Filter
Phase-Detector
Charge-Pump
3
R=1…8
fsys
Divide by R
Figure 16 RF PLL
Selection of a distinct operational frequency band is done via the SFR control bits
RFPLLA. The overall division factor of the PLL-loop is determined by the content of the
SFR control bits RFPLLRx and RFPLLSx, which control a programmable tri-modulus
divider and a reference frequency divider. Depending on the configuration of the multi-
channel feature, the effective source of the control bits RFPLLRx can either be
RFPLLR1, RFPLLR2 or RFPLLR3 and the source of the control bits RFPLLSx can be
either RFPLLS1, RFPLLS2 or RFPLLS3.
Data Sheet
28
Version 4.0, 2007-06-01
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