Timing Chart 3-3
Normal-speed PB
MNT3
t = Dependent on error
condition
C1 correction
MNT1
MNT0
C2 correction
CXD3017Q
Strobe
Strobe
§3-4. DA Interface
• The CXD3017Q's DA interface is as follows:
Interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first.
When LRCK is high, the data is for the left channel.
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