CXD2586R/-1
Pin
No.
Symbol
I/O
Description
116 SRDR O 1, 0 Sled drive output.
117 SFON O 1, 0 Sled drive output.
118 TFDR O 1, 0 Tracking drive output.
119 TRON O 1, 0 Tracking drive output.
120 TRDR O 1, 0 Tracking drive output.
121 TFON O 1, 0 Tracking drive output.
122 FFDR O 1, 0 Focus drive output.
123 FRON O 1, 0 Focus drive output.
124 FRDR O 1, 0 Focus drive output.
125 FFON O 1, 0 Focus drive output.
126 DVDD3
Digital power supply.
127 VCOO O 1, 0 Analog EFM PLL oscillation circuit output.
128 VCOI
I
Analog EFM PLL oscillation circuit input. flock = 8.6436MHz.
129 TEST
I
Test pin. Normally fixed to low.
130 DVSS3
Digital GND.
131 TES2
I
Test pin. Normally fixed to low.
132 TES3
I
Test pin. Normally fixed to low.
134 PDO
O 1, Z, 0 Analog EFM PLL charge pump output.
135 VCKI
I
Variable pitch clock input from the external VCO. fcenter = 16.9344MHz.
136 V16M O 1, 0 Wide-band EFM PLL VCO2 oscillation output.
137 AVDD2
Analog power supply.
138 IGEN
I
Operational amplifier current source reference resistance connection.
139 AVSS2
Analog GND.
140 ADIO O
Operational amplifier output.
141 RFC
I
RF signal LPF time constant capacitor connection.
142 RFDC I
RF signal input.
143 CE
I
Center servo analog input.
144 TE
I
Tracking error signal input.
∗ In the 144-pin LQFP, the following pins are NC:
Pins 17, 30, 44, 61, 90, 100, 109, and 133
Notes) • The 64-bit slot is an LSB first, two's complement output. The 48-bit slot is an MSB first, two's
complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the negative pulse for the frame sync obtained from the EFM signal. It is the signal before
sync protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion protection timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.
• C2PO represents the data error status.
• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
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