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STA335ML View Datasheet(PDF) - STMicroelectronics

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STA335ML Datasheet PDF : 20 Pages
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Applications
5
Applications
STA335ML
5.1
Applications schematic
Figure 10 on the next page shows the schematic of a typical application for the STA335ML.
Concerning the power supplies, take care when designing the PCB layout. In particular, the
3.3-Ω resistors on the digital supplies (VDD_DIG) must be placed as close as possible to
the device. This helps to prevent parasitic oscillation in the digital part of the device due to
the inductive tracks of the PCB. The same rule applies for all the decoupling capacitors in
order to limit any spikes on the supply pins.
5.2
Internal voltage reference
An embedded voltage regulator produces the reference voltages for the DMOS bridge
driver. It requires two 100 nF capacitors to keep the regulator stable. The capacitors should
be place close to the pins.
Figure 8. Reference voltage block diagram
VCC_REG
100 nF
VSS_REG
VDD_REG
100 nF
GND_REG
Regulator
Input
level
shifter
I2S
interface
Driver P
Driver N
VCC
GND
5.3
PLL filter schematic
It is recommended to use the circuit in Figure 9 below for the PLL loop filter to achieve the
best performance from the device in general application. Note that the ground of this filter
scheme has to be connected to the ground of the PLL without any resistive path.
Concerning the component values, please take into account that the greater is the filter
bandwidth, the less is the lock time but the higher is the PLL output jitter.
Figure 9. PLL applications schematic
FILTER_PLL
2k2
680 pF
Ferrite bead 4.7 nF
100 pF
GND_DIG
GND_PLL
12/20
Doc ID 17638 Rev 4
 

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