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STA333BWQS13TR View Datasheet(PDF) - STMicroelectronics

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STA333BWQS13TR Datasheet PDF : 71 Pages
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STA333BWQS
Register description
Note:
To the left of the arrow is the processing channel. When using channel output mapping, any
of the three processing channel outputs can be used for any of the three inputs.
Figure 9. OCFG = 00 (default value)
Half
Bridge
Half
Bridge
Half
Bridge
Half
Bridge
OUT1A
OUT1B
OUT2A
Channel 1
Channel 2
OUT2B
OUT3A
OUT3B LPF
LineOut 1
OUT4A
OUT4B LPF
LineOut 2
Figure 10. OCFG = 01
Half
Bridge
Half
Bridge
Half
Bridge
Half
Bridge
OUT1A
OUT1B
OUT2A
OUT2B
Channel 1
Channel 2
Channel 3
Figure 11. OCFG = 10
Half
Bridge
Half
Bridge
Half
Bridge
Half
Bridge
OUT1A
OUT1B
OUT2A
Channel 1
Channel 2
OUT2B
OUT3A
OUT3B
EAPD
Power
Device
Channel 3
Figure 12. OCFG = 11
Half
Bridge
OUT1A
Half
Bridge
OUT1B
Half
Bridge
Half
Bridge
OUT2A
OUT2B
Channel 3
OUT3A
OUT3B
Channel 1
OUT4A
OUT4B
Channel 2
STA333BWQS can be configured to support different output configurations. For each PWM
output channel a "PWM slot" is defined. PWM slot is always 1 / (8 x Fs) seconds length. The
PWM slot define the maximum extension for PWM rise and fall edge, that is, rising edge as
far as the falling edge cannot range outside PWM slot boundaries.
Figure 13. STA333BWQS output mapping scheme
DDX™
modulator
DDX1A
DDX1B
OUT1A
DDX2A
DDX2B
DDX3A
DDX3B
OUT1B
OUT2A
DDX4A
DDX4B
OUT2B
REMAP
OUT3A
OUT3B
OUT4A
Power
Bridge
OUT4B
OUT1A
OUT1B
OUT2A
OUT2B
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