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STA333BWQS13TR View Datasheet(PDF) - STMicroelectronics

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STA333BWQS13TR Datasheet PDF : 71 Pages
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Register description
STA333BWQS
6.2.4
6.2.5
Table 20. Supported serial audio input formats for LSB-first (SAIFB = 1) (continued)
BICKI
SAI [3:0]
SAIFB
Interface Format
0000
0100
1000
1100
1
I2S 24-bit data
1
I2S 20-bit data
1
I2S 18-bit data
1
LSB first I2S 16-bit data
0001
1
Left-justified 24-bit data
0101
1
Left-justified 20-bit data
64fs
1001
1
Left-justified 18-bit data
1101
1
Left-justified 16-bit data
0010
1
Right-justified 24-bit data
0110
1
Right-justified 20-bit data
1010
1
Right-justified 18-bit data
1110
1
Right-justified 16-bit data
Delay serial clock enable
Table 21. Delay serial clock enable
Bit R/W RST
Name
5
R/W
0
DSCKE
Description
0: no serial clock delay
1: serial clock delay by 1 core clock cycle to tolerate
anomalies in some I2S master devices
Channel input mapping
Table 22. Channel input mapping
Bit R/W RST
Name
6
R/W
0
C1IM
7
R/W
1
C2IM
Description
0: processing channel 1 receives Left I2S Input
1: processing channel 1 receives Right I2S Input
0: processing channel 2 receives Left I2S Input
1: processing channel 2 receives Right I2S Input
Each channel received via I2S can be mapped to any internal processing channel via the
Channel Input Mapping registers. This allows for flexibility in processing. The default
settings of these registers map each I2S input channel to its corresponding processing
channel.
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