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STA333BW13TR View Datasheet(PDF) - STMicroelectronics

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STA333BW13TR Datasheet PDF : 67 Pages
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STA333BW
Register description
The external clock frequency provided to the XTI pin must be a multiple of the input sample
frequency (fs).
The relationship between the input clock and the input sample rate is determined by both
the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor
generating the internal clock and the IR bit determines the oversampling ratio used
internally.
Table 10. Input sampling rates
Input sample rate
IR
fs (kHz)
MCS[2:0]
32, 44.1, 48
88.2, 96
176.4, 192
101
100
011
010
001
000
00 576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs
01 NA
64 * fs 128 * fs 192 * fs 256 * fs 384 * fs
1X NA
32 * fs 64 * fs 96 * fs 128 * fs 192 * fs
Interpolation ratio select
Table 11. Internal interpolation ratio
Bit R/W RST
Name
Description
4:3 R/W 00
IR [1:0]
Selects internal interpolation ratio based on input I2S
sample frequency
The STA333BW has variable interpolation (oversampling) settings such that internal
processing and FFX output rates remain consistent. The first processing block interpolates
by either 2-times or 1-time (pass-through) or provides a 2-times downsample. The
oversampling ratio of this interpolation is determined by the IR bits.
Table 12. IR bit settings as a function of input sample rate
Input sample rate fs (kHz)
IR
1st stage interpolation ratio
32
44.1
48
88.2
96
176.4
192
00
2-times oversampling
00
2-times oversampling
00
2-times oversampling
01
Pass-through
01
Pass-through
10
2-times downsampling
10
2-times downsampling
Doc ID 13773 Rev 3
23/67
 

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