STA333W
Register description
6.1.3
Channel input mapping
Table 20. Channel input mapping
Bit
R/W RST
Name
6
R/W 0
C1IM
7
R/W 0
C2IM
Description
0: processing channel 1 receives left I2S input
1: processing channel 1 receives right I2S input
0: processing channel 2 receives left I2S input
1: processing channel 2 receives right I2S input
Each channel received via I2S can be mapped to any internal processing channel via the
channel input mapping registers. This allows for flexibility in processing. The default settings
of these registers map each I2S input channel to its corresponding processing channel.
Configuration register C (addr 0x02)
D7
OCRB
1
D6
Reserved
0
D5
CSZ3
0
D4
CSZ2
1
D3
CSZ1
0
D2
CSZ0
1
D1
OM1
1
D0
OM0
1
DDX power output mode
Table 21. DDX power output mode
Bit
R/W RST
Name
Description
0
R/W 1
OM0
1
R/W 1
OM1
The DDX power output mode selects the configuration
of the DDX output:
00: drop compensation
01: discrete output stage: tapered compensation
10: full-power mode
11: variable drop compensation (CSZx bits)
DDX compensation pulse size register
Table 22. DDX compensating pulse size
Bit
R/W RST
Name
Description
2
R/W 1
CSZ0
3
R/W 0
CSZ1
4
R/W 1
CSZ2
5
R/W 0
CSZ3
When OM[1:0] = 11, this register determines the size of
the DDX compensating pulse from 0 to 15 clock periods:
0000: 0 ns (0 ticks) compensating pulse size
0001: 20 ns (1 tick) clock period compensating pulse
size
.....
1111: 300 ns (15 ticks) clock period compensating pulse
size
Doc ID 13365 Rev 2
27/49