Serial digital audio interface (SAI)
8
Serial digital audio interface (SAI)
STA330
8.1
Specifications
The serial-to-parallel interface and the parallel-to-serial interface can have different
sampling rates.
The following terms are used in this section:
" BICLK active edge: Pins SDATAI, SDATAO, LRCLKI, LRCLKO always change
synchronously with BITCLK active edges. The active edge can be configured to a rising
or falling edge via register programming.
" BICLK strobe edge: Pins SDATAI, SDATAO, LRCLKI, LRCLKO should be stable near
BICLK strobe edges, the slave device is able to use strobe edges to latch serial data
internally.
8.2
Master mode
In this mode pins BICLKI/BICLKO and pins LRCLKI/LRCLKO are configured as outputs.
Figure 10. Master mode
BICLKI/
BICLKO
LRCLKI/
LRCLKO
SDATAO
tDL
tDDA
SDATAI
tDST
tDHT
Table 14. Master mode
Symbol
Parameter
Min Typ Max Unit
tDL
LRCLKI/LRCLKO propagation delay from BICLK active
edge
0
tDDA SDATAI propagation delay from BICLKI/O active edge 0
tDST Sdatao setup time to BICLKI/O strobing edge
10
tDHT Sdatao hold time from BICLKI/O strobing edge
10
10 ns
15 ns
ns
ns
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