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STA016A View Datasheet(PDF) - STMicroelectronics

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STA016A Datasheet PDF : 43 Pages
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STA016A
Table 20. .
Bit
CF8
CF9
CF10
CF11
CF12
CF13
CF14
CF15
Comment
Relative synchro :
0 : synchro with first data bit
1 : synchro one bit before first data bit
Data reception configuration :
0 : LSB first
1 : MSB first
Arithmetic type of the reception :
0 : unsigned data
1 : signed data
Bit to select the reference clock used to
generate BCK if clocks are in output
(CF2=1 & CF5=1). Otherwise this bit is
useless.
0 : SYSCK
1 : PCMCK
Reserved : to be set to 1
Reserved : to be set to 1
Reserved : to be set to 0
Reserved : to be set to 0
6.7.4 I_AUDIO_CONFIG_3 :
b7 b6 b5 b4 b3 b2 b1 b0
LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0
Address : 0x5D (93)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_4 register description..
6.7.5 I_AUDIO_CONFIG_4 :
b7 b6 b5 b4 b3 b2 b1 b0
LR15 LR14 LR13 LR12 LR11 LR10 LR9 LR8
Address : 0x5E (94)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, this register is used to config-
urate LR clocks (CD_LRCK & BS_LRCK) of CD & BS
input interfaces in audio mode.
Table 21.
Bit fields
LR[5:0]
LR[11:6]
LR[15:12]
Comment
Length-1 of phase 1 of LR clocks
CD_LRCK & BS_LRCK.
Max value is 31.
Length-1 of phase 2 of LR clocks
CD_LRCK & BS_LRCK.
Max value is 31.
Reserved : to be set to 0
6.7.6 I_AUDIO_CONFIG_5:
b7 b6 b5 b4 b3 b2 b1 b0
MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0
Address : 0x5F (95)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_8 register description.
6.7.7 I_AUDIO_CONFIG_6 :
b7 b6 b5 b4 b3 b2 b1 b0
MA1 MA1 MA1 MA1 MA1 MA1 MA9 MA8
5
4
3
2
1
0
Address : 0x60 (96)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_8 register description..
6.7.8 I_AUDIO_CONFIG_7 :
b7 b6 b5 b4 b3 b2 b1 b0
MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16
Address : 0x61 (97)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_8 register description..
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