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74LVTH16244ADGGRG4 View Datasheet(PDF) - Texas Instruments

Part Name74LVTH16244ADGGRG4 TI
Texas Instruments TI
Description3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
74LVTH16244ADGGRG4 Datasheet PDF : 19 Pages
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SN54LVTH16244A, SN74LVTH16244A
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS142T – MAY 1992 – REVISED NOVEMBER 2006
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500 S1
500
6V
Open
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
6V
GND
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Input
LOAD CIRCUIT
tw
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
2.7 V
0V
Timing Input
Data Input
1.5 V
2.7 V
0V
tsu
th
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
2.7 V
0V
Input
1.5 V
1.5 V
2.7 V
0V
tPLH
Output
1.5 V
tPHL
1.5 V
VOH
VOL
tPHL
tPLH
Output
1.5 V
VOH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
1.5 V
1.5 V
2.7 V
0V
tPZL
Output
Waveform 1
S1 at 6 V
(see Note B)
1.5 V
tPLZ
3V
VOL + 0.3 V VOL
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
tPHZ
VOH − 0.3 V VOH
0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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DESCRIPTION/ORDERING INFORMATION
The 'LVTH16244A devices are 16-bit buffers and line drivers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical active-low output-enable (OE) inputs.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

FEATURES
• Members of the Texas Instruments Widebus™ Family
• State-of-the-Art Advanced BiCMOS
   Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation
• Support Mixed-Mode Signal Operation
   (5-V Input and Output Voltages With 3.3-V VCC)
• Support Unregulated Battery Operation Down to 2.7 V
• Typical VOLP (Output Ground Bounce)
   <0.8 V at VCC = 3.3 V, TA = 25°C
• Ioff and Power-Up 3-State Support Hot Insertion
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 500 mA Per JESD 17
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)
   – 200-V Machine Model (A115-A)

 

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