T89C51RD2-3CFC-M View Datasheet(PDF) - Atmel Corporation
Part Name
Description
View to exact match
T89C51RD2-3CFC-M Datasheet PDF : 86 Pages
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T89C51RD2
Mnemonic
Reset
ALE/PROG
PSEN
EA
XTAL1
XTAL2
Pin Number
DIL LCC VQFP 1.4
17 19
13
9
10
4
30 33
27
29 32
26
31 35
29
19 21
15
18 20
14
Type
O
I/O
O (I)
O
I
I
O
Name and Function
RD (P3.7): External data memory read strobe
Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to VSS permits a power-on reset
using only an external capacitor to VCC. This pin is an output when the hardware
watchdog forces a system reset.
Address Latch Enable/Program Pulse: Output pulse for latching the low byte
of the address during an access to external memory. In normal operation, ALE
is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,
and can be used for external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory. This pin is also the program
pulse input (PROG) during Flash programming. ALE can be disabled by setting
SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches.
Program Store ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
External Access Enable: EA must be externally held low to enable the device
to fetch code from external program memory locations 0000H to FFFFH (RD).
If security level 1 is programmed, EA will be internally latched on Reset.
Crystal 1: Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
Crystal 2: Output from the inverting oscillator amplifier
8
Rev. F - 15 February, 2001
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