PIC32MX110F016B-40V/ML View Datasheet(PDF) - Microchip Technology

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PIC32MX110F016B-40V/ML

32-bit Microcontrollers (up to 256 KB Flash and 64 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

Microchip Technology 

TABLE 4-9: ADC REGISTER MAP

Bits

Register

Name

31/15 30/14 29/13 28/12 27/11 26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

9000 AD1CON1(1) 31:16

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

15:0 ON

—

SIDL

—

—

FORM<2:0>

SSRC<2:0>

CLRASAM —

ASAM SAMP DONE

9010 AD1CON2(1) 31:16

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

15:0

VCFG<2:0>

OFFCAL —

CSCNA

—

—

BUFS

—

SMPI<3:0>

BUFM ALTS

9020 AD1CON3(1) 31:16

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

15:0 ADRC

—

—

SAMC<4:0>

ADCS<7:0>

9040 AD1CHS(1) 31:16 CH0NB

—

—

—

CH0SB<3:0>

CH0NA

—

—

—

CH0SA<3:0>

15:0 —

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

9050 AD1CSSL(1) 31:16

—

—

—

—

—

—

—

15:0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9

—

CSSL8

—

CSSL7

—

CSSL6

—

CSSL5

—

CSSL4

—

CSSL3

—

CSSL2

—

CSSL1

—

CSSL0

31:16

9070 ADC1BUF0

15:0

ADC Result Word 0 (ADC1BUF0<31:0>)

31:16

9080 ADC1BUF1

15:0

ADC Result Word 1 (ADC1BUF1<31:0>)

31:16

9090 ADC1BUF2

15:0

ADC Result Word 2 (ADC1BUF2<31:0>)

31:16

90A0 ADC1BUF3

15:0

ADC Result Word 3 (ADC1BUF3<31:0>)

31:16

90B0 ADC1BUF4

15:0

ADC Result Word 4 (ADC1BUF4<31:0>)

31:16

90C0 ADC1BUF5

15:0

ADC Result Word 5 (ADC1BUF5<31:0>)

31:16

90D0 ADC1BUF6

15:0

ADC Result Word 6 (ADC1BUF6<31:0>)

31:16

90E0 ADC1BUF7

15:0

ADC Result Word 7 (ADC1BUF7<31:0>)

31:16

90F0 ADC1BUF8

15:0

ADC Result Word 8 (ADC1BUF8<31:0>)

31:16

9100 ADC1BUF9

15:0

ADC Result Word 9 (ADC1BUF9<31:0>)

31:16

9110 ADC1BUFA

15:0

ADC Result Word A (ADC1BUFA<31:0>)

31:16

9120 ADC1BUFB

15:0

ADC Result Word B (ADC1BUFB<31:0>)

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for details.

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