datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ISPLSI2064E-200LT100 View Datasheet(PDF) - Lattice Semiconductor

Part Name
Description
View to exact match
ISPLSI2064E-200LT100
Lattice
Lattice Semiconductor Lattice
ISPLSI2064E-200LT100 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
ispLSI 2064E Timing Model
Specifications ispLSI 2064E
I/O Cell
Ded. In
I/O Pin
(Input)
#21
I/O Delay
#20
Reset
GRP
GRP
#22
#45
GLB
Feedback
Comb 4 PT Bypass #23
Reg 4 PT Bypass
#24
GLB Reg Bypass
#28
20 PT
XOR Delays
#25, 26, 27
GLB Reg
Delay
D
Q
RST
#29, 30,
31, 32
Y0,1,2
GOE 0,1
#43, 44
#42
Control RE
PTs OE
#33, 34, CK
35
Derivations of tsu, th and tco from the Product Term Clock
tsu
= Logic + Reg su - Clock (min)
= (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
= (#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
3.1ns = (0.5 + 0.6 + 2.9) + (1.2) - (0.5 + 0.6 + 1.0)
th
= Clock (max) + Reg h - Logic
= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
= (#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
3.4ns = (0.5 + 0.6 + 4.0) + (2.3) - (0.5 + 0.6 + 2.9)
tco
= Clock (max) + Reg co + Output
= (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
= (#20 + #22 + #35) + (#31) + (#36 + #38)
7.9ns = (0.5 + 0.6 + 4.0) + (0.3) + (0.9 + 1.6)
Table 2- 0042A-2064e
Note: Calculations are based upon timing specifications for the ispLSI 2064E-200L.
ORP
I/O Cell
ORP Bypass
#37
ORP
Delay
#36
#38,
39
I/O Pin
(Output)
#40, 41
0491/2064
7
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]